1. Field of Invention
The present invention relates to a digital-to-analog (D/A) conversion device. More specifically, the present invention relates to a D/A conversion device without using level-shift units.
2. Description of Related Art
A digital-to-analog (D/A) converter is usually used in converting digital input data into analog output data. FIG. 1 is a schematic block diagram illustrating a conventional D/A converter. With reference to FIG. 1, the D/A converter includes a data-latch unit 101, a D/A conversion unit 104, level-shift units 108 and 109, switches S1 and S2 and a unity-gain amplifier 107. The data-latch unit 101 includes a first data-latch 102 and a second data-latch 103. The D/A conversion unit 104 includes a reference voltage supply 105 and a switch control unit 106.
FIG. 1A is a schematic timing sequence chart describing the non-overlap clock signals CK1 and CK2 used in FIG. 1. With reference to FIG. 1 and FIG. 1A, during phase 1 (i.e. when clock signal CK1 is in a high level phase), a digital input data (Din) is read into the data-latch 102, and a previous digital input data is still latched in the data-latch 103. At this moment, the switch S2 is controlled by the clock signal CK1 and is turned on. Therefore, the previous digital input data, which was latched in the data-latch 103 earlier, is sent to the switch control unit 106 via the level-shift unit 109 and the switch S2 so as to perform D/A conversion. The corresponding analog voltage (from the reference voltage supply 105) will be sent to the unity-gain amplifier 107 to serve as the analog output data Aout.
During phase 2 (i.e. when the clock signal CK2 is in a high level phase), a next digital input data (Din) will be read into the data-latch 103, and the digital data inputted during phase 1 is still latched in the data-latch 102. At this time, the switch S1 is controlled by the clock signal CK2 and is turned on. Therefore, the digital input data, which was input during phase 1 and was latched in the data-latch 102, is sent to the switch control unit 106 via the level-shift unit 108 and the switch S1 in order to perform D/A conversion. The corresponding analog voltage (from the reference voltage supply 105) will be sent to the unity-gain amplifier 107 to acquire another analog output data Aout.
The data-latches 102 and 103 both operate on a first voltage VDD1 and a second voltage VSS1. The reference voltage supply 105 operates on a third voltage VDD2 and a fourth voltage VSS2 to provide a plurality of reference voltages for D/A conversion. The level-shift units 108 and 109 are used to increase the voltage level of the digital input data, so that the switches in the switch control unit 106 can be fully turned on. The unity-gain amplifier 107 coupled to a fifth voltage VDD3 and a sixth voltage VSS3 is used to increase the driving ability to output load. For the data-latch unit 101, the conventional voltage VDD1 and VSS1 are always within the range of a small voltage amplitude, and the voltage amplitude is less than the voltages VDD2 and VSS2 (also is less than voltages VDD3 and VSS3). Therefore, the conventional technology has to increase the voltage level of the input data through the level-shift unit. The level-shift unit 108 and the level-shift unit 109 operate at the voltage amplitude of voltages VDD4 and VSS4 (must be not less than the voltage amplitude of voltages VDD2 and VSS2), so that the switches of the switch control unit 106 can be fully turned on or turned off.
FIG. 2 is a schematic block diagram of another conventional D/A converter. With reference to FIG. 2, a data-latch unit 201, a D/A conversion unit 204 and a unity-gain amplifier 207 are included. The data-latch unit 201 includes a first data-latch 202 and a second data-latch 203. The D/A conversion unit 204 includes a reference voltage supply 205 and a switch control unit 206. The timing sequence of the clock signals CK1 and CK2 can be referred to FIG. 1A. When the clock signal CK1 is in a high level, a digital input data (Din) is read into the first data-latch 202, and the previous digital input data is still latched in the second data-latch 203 and is constantly sent to the level-shift unit 208. When the clock signal CK2 is in a high level, the digital input data (Din) is latched in the first data latch 202 and is read into the second data-latch 203 at the same time. The previous digital input data originally latched in the second data latch 203 is then updated and is sent to the level-shift unit 208 at the same time. Since the latched data outputted by the second data-latch 203 operates between the voltages VDD1 and VSS1, which are not enough to drive the switches in the switch control unit 206. Therefore, the level-shift unit 208 converts the digital input data into a higher voltage level, so as to fully turn on or turn off the switches in the switch control unit 206. The D/A conversion unit 204 generates an analog voltage according to the reference voltage supply 205 and the digital code outputted by the level-shift unit 208. Then, the corresponding analog voltage (from the reference voltage supply 205) is sent to the unity-gain amplifier 207 to serve as the analog output data Aout. The unity-gain amplifier 207 is used to increase the driving ability to the output load.
Next, when the clock signal CK1 becomes the high level again, the next new digital input data is read into the data-latch 202, and the previous digital input data is still latched in the second data-latch 203 and is sent to the level-shift unit 208. When the clock signal CK2 becomes the high level again, the next new digital input data is still latched in the first data-latch 202 and is sent to the second data-latch 203 and the level-shift unit 208. And the previous digital input data stored in the data-latch 203 is updated accordingly. Therefore, the D/A conversion unit 204 then outputs a next new analog voltage. Lastly, the new analog voltage is outputted by the unity-gain amplifier 207.
As show in FIG. 2, the data-latches 202 and 203 operate at the voltage VDD1 and voltage VSS1. The reference voltage supply 205 operates at the voltage VDD2 and voltage VSS2. The unity-gain amplifier 207 operates at the voltage VDD3 and voltage VSS3, and the level-shift unit 208 operates at the voltage VDD4 and voltage VSS4. The operation principle of the D/A converter is similar to what is described in FIG. 1. The main difference between FIG. 1 and FIG. 2 is that the data-latches 202 and 203 in the data-latch unit 201 in FIG. 2 are serially connected; therefore, only one level-shift unit 208 is required.
FIG. 3 schematically describes another conventional D/A conversion device. With reference to FIG. 3, the D/A conversion device has multiple channels, wherein each of the channels is equipped with a D/A converter (i.e. DAC1˜DACm), and only a reference voltage supply is used. Take the mth D/A converter (DACm) as the example, a data-latch unit 301, a level-shift unit 309, a D/A conversion unit 305 and a unity-gain amplifier 308 are included. The data-latch unit 301 includes a shift register 302, a first data-latch 303 and a second data latch 304. The D/A conversion unit 305 includes a reference voltage supply 306 and a switch control unit 307. The second control signal CT2 is used to control the data-latch 304, and the first clock signal CK1 and the first control signal CT1 are used to activate the shift register 302.
FIG. 3A schematically illustrates the timing sequence relations of the signals in FIG. 3. Refer to FIG. 3 and FIG. 3A, the shift registers of the D/A converters DAC1˜DACm sequentially transmit the first control signal CT1 according to the timing sequence of the first clock signal CK1. Whenever the first control signal CT1 is detected as the high level through the first clock signal CK1 in the high level, the shift register 302 outputs a first enabling signal to the first data-latch 303. Therefore, the first digital input data Din is then received and latched in the first data-latch 303. In other words, in the D/A converters DAC1˜DACm, the shift registers output a series of enabling signals to the first data-latches according to the clock signal CK1; and a series of digital input data Dins is received and latched in the first data-latches in sequence. When the serially connected digital input data Dins is completely received and latched in the first data-latches, the second control signal CT2 is then transformed into the high level. Whenever the second control signal CT2 is detected as the high level through the first clock signal CK1 in the high level, the data latched in the first data-latch (for example, 303) is then sent to and latched in the second data-latch (for example, 304). The level-shift units (for example 309) transform the digital input data into higher voltage level, so as to turn on/off the switches in the switch control units (for example, 307). The switch control units select the corresponding reference voltages outputted by the reference voltage supply 306 according to the digital codes outputted by the level-shift units, so as to generate analog voltages. The unity-gain amplifier (for example, 308) is used to increase the driving ability to the output load.
Next, the first control signal CT1 is transformed again and is detected by the first clock signal CK1 when the first control signal CT1 is in the high level, accordingly, the data in the first data-latches is updated and latched. Then, the above described data-latching operation is repeated. The principle of the D/A conversion operation is similar to the descriptions of FIG. 1 and FIG. 2. The main difference is that the device in FIG. 3 can latch a plurality of digital input data in the first data-latches and the first data-latch 303 latches the digital input data Din according to the command of the shift register 302. As shown in FIG. 3, the data-latches 302, 303 and the shift register 301 operate at the voltage VDD1 and the voltage VSS1, while the reference voltage 306 operates at the voltage VDD2 and voltage VSS2. The unity-gain amplifier 308 operates at the voltage VDD3 and voltage VSS3, and the level-shift unit 309 operates at the voltage VDD4 and the voltage VSS4.
In the conventional technology as shown in FIG. 1, FIG. 2 and FIG. 3, since the voltages VDD1<VDD2≦VDD4≦VDD3, and the voltages VSS3≦VSS4≦VSS2≦VSS1, therefore, the conventional technology needs the level-shift units to increase the voltage level of the digital input data, so as to fully turn on/turn off the switches in the switch control units to complete the D/A conversion.